2 Job openings found

Exp: 7 to 15 years Work location: Bangalore/Remote   Key Responsibilities: Work with system architect to understand the requirements and design efficient RTL implementations targeting FPGAs. Translate MATLAB models to RTL for hardware realization MATLAB/Simulink based modelling, simulation and conversion to RTL Develop RTL architecture and microarchitecture based on algorithm requirements Implement RTL (Verilog/VHDL/SystemVerilog) for blocks like ORAN, ...

Designation - Lead/ASIC Verification Engineer Exp- 4-8-12 Years Job Location - Bangalore, Ahmedabad, Chennai Pune, Noida, Hyderabad   Required skills : Experience working of SV and UVM methodology. Experience of at least one industry standard protocols like  Ethernet, PCIe, MIPI, USB or similar is required. Must have executed at-least 2 SoC Verification projects.